The following publications are possibly variants of this publication:
- Combinational and sequential logic optimization by redundancy addition and removalLuis Entrena-Arrontes, Kwang-Ting Cheng. tcad, 14(7):909-916, 1995. [doi]
- On the Optimization Power of Redundancy Addition and Removal for Sequential Logic OptimizationEnrique San Millán, Luis Entrena, José Alberto Espejo. dsdm 2001: 292-299 [doi]
- Logic optimization by an improved sequential redundancy addition and removal techniquesUwe Gläser, Kwang-Ting Cheng. aspdac 1995: [doi]
- Generalized reasoning scheme for redundancy addition and removal logic optimizationJosé Alberto Espejo, Luis Entrena, Enrique San Millán, Emilio Olías. date 2001: 391-397 [doi]
- Theoretical comparison between sequential redundancy addition and removal and retiming optimization techniquesEnrique San Millán, Luis Entrena, José Alberto Espejo, Celia López. jsa, 49(12-15):529-541, 2003. [doi]
- On the Optimization Power of Redundancy Addition and Removal Techniques for Sequential CircuitsEnrique San Millán, Luis Entrena, José Alberto Espejo. iccad 2001: 91-94 [doi]
- Redundancy removal for sequential circuits without reset statesKwang-Ting Cheng. tcad, 12(1):13-24, 1993. [doi]