Challenges in low-power analog circuit design for sub-28nm CMOS technologies

Amr Fahim. Challenges in low-power analog circuit design for sub-28nm CMOS technologies. In Yuan Xie 0001, Tanay Karnik, Muhammad M. Khellah, Renu Mehra, editors, International Symposium on Low Power Electronics and Design, ISLPED'14, La Jolla, CA, USA - August 11 - 13, 2014. pages 123-126, ACM, 2014. [doi]

@inproceedings{Fahim14-0,
  title = {Challenges in low-power analog circuit design for sub-28nm CMOS technologies},
  author = {Amr Fahim},
  year = {2014},
  doi = {10.1145/2627369.2631639},
  url = {http://doi.acm.org/10.1145/2627369.2631639},
  researchr = {https://researchr.org/publication/Fahim14-0},
  cites = {0},
  citedby = {0},
  pages = {123-126},
  booktitle = {International Symposium on Low Power Electronics and Design, ISLPED'14, La Jolla, CA, USA - August 11 - 13, 2014},
  editor = {Yuan Xie 0001 and Tanay Karnik and Muhammad M. Khellah and Renu Mehra},
  publisher = {ACM},
  isbn = {978-1-4503-2975-0},
}