Challenges in low-power analog circuit design for sub-28nm CMOS technologies

Amr Fahim. Challenges in low-power analog circuit design for sub-28nm CMOS technologies. In Yuan Xie 0001, Tanay Karnik, Muhammad M. Khellah, Renu Mehra, editors, International Symposium on Low Power Electronics and Design, ISLPED'14, La Jolla, CA, USA - August 11 - 13, 2014. pages 123-126, ACM, 2014. [doi]

Abstract

Abstract is missing.