Buffer-integrated-Cache: a cost-effective SRAM architecture for handheld and embedded platforms - researchr publication authors

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Carlos Flores Fajardo, Zhen Fang, Ravi Iyer, German Fabila Garcia, Seung Eun Lee, Li Zhao. Buffer-integrated-Cache: a cost-effective SRAM architecture for handheld and embedded platforms. In Leon Stok, Nikil D. Dutt, Soha Hassoun, editors, Proceedings of the 48th Design Automation Conference, DAC 2011, San Diego, California, USA, June 5-10, 2011. pages 966-971, ACM, 2011. [doi]

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