Voltage droop reduction using throttling controlled by timing margin feedback

Michael S. Floyd, Alan J. Drake, Robert W. Berry, Harold Chase, Richard L. Willaman, Jarom Pena. Voltage droop reduction using throttling controlled by timing margin feedback. In Symposium on VLSI Circuits, VLSIC 2012, Honolulu, HI, USA, June 13-15, 2012. pages 96-97, IEEE, 2012. [doi]

References

No references recorded for this publication.

Cited by

No citations of this publication recorded.