A 6.0-GS/s Time-Interleaved DAC Using an Asymmetric Current-Tree Summation Network and Differential Clock Timing Calibration - researchr publication authors

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Yushen Fu, Chengyu Huang, Limeng Sun, Weiguang Meng, Xueqing Li, Huazhong Yang. A 6.0-GS/s Time-Interleaved DAC Using an Asymmetric Current-Tree Summation Network and Differential Clock Timing Calibration. IEEE Trans. VLSI Syst., 31(2):199-209, February 2023. [doi]

This author has not been identified. Look up 'Yushen Fu' in GoogleThis author has not been identified. Look up 'Chengyu Huang' in GoogleThis author has not been identified. Look up 'Limeng Sun' in GoogleThis author has not been identified. Look up 'Weiguang Meng' in GoogleThis author has not been identified. Look up 'Xueqing Li' in GoogleThis author has not been identified. Look up 'Huazhong Yang' in Google

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