A 6.0-GS/s Time-Interleaved DAC Using an Asymmetric Current-Tree Summation Network and Differential Clock Timing Calibration - researchr publication

researchr

You are not signed in
Sign in
Sign up

Yushen Fu, Chengyu Huang, Limeng Sun, Weiguang Meng, Xueqing Li, Huazhong Yang. A 6.0-GS/s Time-Interleaved DAC Using an Asymmetric Current-Tree Summation Network and Differential Clock Timing Calibration. IEEE Trans. VLSI Syst., 31(2):199-209, February 2023. [doi]

Abstract is missing.

runs on WebDSL