Yushen Fu, Chengyu Huang, Limeng Sun, Weiguang Meng, Xueqing Li, Huazhong Yang. A 6.0-GS/s Time-Interleaved DAC Using an Asymmetric Current-Tree Summation Network and Differential Clock Timing Calibration. IEEE Trans. VLSI Syst., 31(2):199-209, February 2023. [doi]
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