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On-chip leakage monitor circuit to scan optimal reverse bias voltage for adaptive body-bias circuit under gate induced drain leakage effect

M. Fujii, H. Suzuki, H. Notani, H. Makino, H. Shinohara. On-chip leakage monitor circuit to scan optimal reverse bias voltage for adaptive body-bias circuit under gate induced drain leakage effect. In William Redman-White, Anthony J. Walton, editors, ESSCIRC 2008 - 34th European Solid-State Circuits Conference, Edinburgh, Scotland, UK, 15-19 September 2008. pages 258-261, IEEE, 2008. [doi]

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M. Fujii

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H. Suzuki

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H. Notani

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H. Makino

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H. Shinohara

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