M. Fujii, H. Suzuki, H. Notani, H. Makino, H. Shinohara. On-chip leakage monitor circuit to scan optimal reverse bias voltage for adaptive body-bias circuit under gate induced drain leakage effect. In William Redman-White, Anthony J. Walton, editors, ESSCIRC 2008 - 34th European Solid-State Circuits Conference, Edinburgh, Scotland, UK, 15-19 September 2008. pages 258-261, IEEE, 2008. [doi]
@inproceedings{FujiiSNMS08,
title = {On-chip leakage monitor circuit to scan optimal reverse bias voltage for adaptive body-bias circuit under gate induced drain leakage effect},
author = {M. Fujii and H. Suzuki and H. Notani and H. Makino and H. Shinohara},
year = {2008},
doi = {10.1109/ESSCIRC.2008.4681841},
url = {https://doi.org/10.1109/ESSCIRC.2008.4681841},
researchr = {https://researchr.org/publication/FujiiSNMS08},
cites = {0},
citedby = {0},
pages = {258-261},
booktitle = {ESSCIRC 2008 - 34th European Solid-State Circuits Conference, Edinburgh, Scotland, UK, 15-19 September 2008},
editor = {William Redman-White and Anthony J. Walton},
publisher = {IEEE},
isbn = {978-1-4244-2361-3},
}