Koichi Fujiwara, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa. Interconnection-Delay and Clock-Skew Estimate Modelings for Floorplan-Driven High-Level Synthesis Targeting FPGA Designs. IEICE Transactions, 99-A(7):1294-1310, 2016. [doi]
@article{FujiwaraKYT16,
title = {Interconnection-Delay and Clock-Skew Estimate Modelings for Floorplan-Driven High-Level Synthesis Targeting FPGA Designs},
author = {Koichi Fujiwara and Kazushi Kawamura and Masao Yanagisawa and Nozomu Togawa},
year = {2016},
url = {http://search.ieice.org/bin/summary.php?id=e99-a_7_1294},
researchr = {https://researchr.org/publication/FujiwaraKYT16},
cites = {0},
citedby = {0},
journal = {IEICE Transactions},
volume = {99-A},
number = {7},
pages = {1294-1310},
}