The following publications are possibly variants of this publication:
- Clock skew estimate modeling for FPGA high-level synthesis and its applicationKoichi Fujiwara, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa. asicon 2015: 1-4 [doi]
- A Floorplan-Driven High-Level Synthesis Algorithm for Multiplexer Reduction Targeting FPGA DesignsKoichi Fujiwara, Kazushi Kawamura, Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa. ieicet, 98-A(7):1392-1405, 2015. [doi]
- A floorplan-aware high-level synthesis algorithm for multiplexer reduction targeting FPGA designsKoichi Fujiwara, Shin-ya Abe, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa. apccas 2014: 244-247 [doi]