Interconnection-Delay and Clock-Skew Estimate Modelings for Floorplan-Driven High-Level Synthesis Targeting FPGA Designs - researchr publication

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Koichi Fujiwara, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa. Interconnection-Delay and Clock-Skew Estimate Modelings for Floorplan-Driven High-Level Synthesis Targeting FPGA Designs. IEICE Transactions, 99-A(7):1294-1310, 2016. [doi]

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