2 Fully-Digital Compute-in-Memory Macro Supporting INT12 × INT12 with a Parallel-MAC Architecture and Foundry 6T-SRAM Bit Cell

Hidehiro Fujiwara, Haruki Mori, Wei-Chang Zhao, Kinshuk Khare, Cheng-En Lee, Xiaochen Peng, Vineet Joshi, Chao-Kai Chuang, Shu-Huan Hsu, Takeshi Hashizume, Toshiaki Naganuma, Chen-Hung Tien, Yao-Yi Liu, Yen-Chien Lai, Chia-Fu Lee, Tan-Li Chou, Kerem Akarvardar, Saman Adham, Yih Wang, Yu-Der Chih, Yen-Huei Chen, Hung-Jen Liao, Tsung-Yung Jonathan Chang. 2 Fully-Digital Compute-in-Memory Macro Supporting INT12 × INT12 with a Parallel-MAC Architecture and Foundry 6T-SRAM Bit Cell. In IEEE International Solid-State Circuits Conference, ISSCC 2024, San Francisco, CA, USA, February 18-22, 2024. pages 572-574, IEEE, 2024. [doi]

Authors

Hidehiro Fujiwara

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Haruki Mori

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Wei-Chang Zhao

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Kinshuk Khare

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Cheng-En Lee

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Xiaochen Peng

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Vineet Joshi

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Chao-Kai Chuang

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Shu-Huan Hsu

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Takeshi Hashizume

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Toshiaki Naganuma

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Chen-Hung Tien

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Yao-Yi Liu

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Yen-Chien Lai

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Chia-Fu Lee

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Tan-Li Chou

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Kerem Akarvardar

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Saman Adham

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Yih Wang

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Yu-Der Chih

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Yen-Huei Chen

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Hung-Jen Liao

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Tsung-Yung Jonathan Chang

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