Hidehiro Fujiwara, Haruki Mori, Wei-Chang Zhao, Kinshuk Khare, Cheng-En Lee, Xiaochen Peng, Vineet Joshi, Chao-Kai Chuang, Shu-Huan Hsu, Takeshi Hashizume, Toshiaki Naganuma, Chen-Hung Tien, Yao-Yi Liu, Yen-Chien Lai, Chia-Fu Lee, Tan-Li Chou, Kerem Akarvardar, Saman Adham, Yih Wang, Yu-Der Chih, Yen-Huei Chen, Hung-Jen Liao, Tsung-Yung Jonathan Chang. 2 Fully-Digital Compute-in-Memory Macro Supporting INT12 × INT12 with a Parallel-MAC Architecture and Foundry 6T-SRAM Bit Cell. In IEEE International Solid-State Circuits Conference, ISSCC 2024, San Francisco, CA, USA, February 18-22, 2024. pages 572-574, IEEE, 2024. [doi]
@inproceedings{FujiwaraMZKLPJCHHNTLLLCAAWCCLC24,
title = {2 Fully-Digital Compute-in-Memory Macro Supporting INT12 × INT12 with a Parallel-MAC Architecture and Foundry 6T-SRAM Bit Cell},
author = {Hidehiro Fujiwara and Haruki Mori and Wei-Chang Zhao and Kinshuk Khare and Cheng-En Lee and Xiaochen Peng and Vineet Joshi and Chao-Kai Chuang and Shu-Huan Hsu and Takeshi Hashizume and Toshiaki Naganuma and Chen-Hung Tien and Yao-Yi Liu and Yen-Chien Lai and Chia-Fu Lee and Tan-Li Chou and Kerem Akarvardar and Saman Adham and Yih Wang and Yu-Der Chih and Yen-Huei Chen and Hung-Jen Liao and Tsung-Yung Jonathan Chang},
year = {2024},
doi = {10.1109/ISSCC49657.2024.10454556},
url = {https://doi.org/10.1109/ISSCC49657.2024.10454556},
researchr = {https://researchr.org/publication/FujiwaraMZKLPJCHHNTLLLCAAWCCLC24},
cites = {0},
citedby = {0},
pages = {572-574},
booktitle = {IEEE International Solid-State Circuits Conference, ISSCC 2024, San Francisco, CA, USA, February 18-22, 2024},
publisher = {IEEE},
isbn = {979-8-3503-0620-0},
}