Inductance model and analysis methodology for high-speed on-chip interconnect - researchr publication authors

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Kaushik Gala, David Blaauw, Vladimir Zolotov, P. M. Vaidya, A. Joshi. Inductance model and analysis methodology for high-speed on-chip interconnect. IEEE Trans. VLSI Syst., 10(6):730-745, 2002. [doi]

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