Kaushik Gala, David Blaauw, Vladimir Zolotov, P. M. Vaidya, A. Joshi. Inductance model and analysis methodology for high-speed on-chip interconnect. IEEE Trans. VLSI Syst., 10(6):730-745, 2002. [doi]
@article{GalaBZVJ02,
title = {Inductance model and analysis methodology for high-speed on-chip interconnect},
author = {Kaushik Gala and David Blaauw and Vladimir Zolotov and P. M. Vaidya and A. Joshi},
year = {2002},
doi = {10.1109/TVLSI.2002.801619},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2002.801619},
tags = {analysis},
researchr = {https://researchr.org/publication/GalaBZVJ02},
cites = {0},
citedby = {0},
journal = {IEEE Trans. VLSI Syst.},
volume = {10},
number = {6},
pages = {730-745},
}