The following publications are possibly variants of this publication:
- Design for hierarchical testability of RTL circuits obtained by behavioral synthesisIndradeep Ghosh, Anand Raghunathan, Niraj K. Jha. tcad, 16(9):1001-1014, 1997. [doi]
- A design for testability technique for RTL circuits using control/data flow extractionIndradeep Ghosh, Anand Raghunathan, Niraj K. Jha. iccad 1996: 329-336 [doi]
- Behavioral Synthesis for Hierarchical Testability of Controller/Data Path Circuits with Conditional BranchesSandeep Bhatia, Niraj K. Jha. iccd 1994: 91-96
- Integration of hierarchical test generation with behavioral synthesis of controller and data path circuitsSandeep Bhatia, Niraj K. Jha. tvlsi, 6(4):608-619, 1998. [doi]