Hans Giesen, Raphael Rubin, Benjamin Gojman, André DeHon. Quality-Time Tradeoffs in Component-Specific Mapping: How to Train Your Dynamically Reconfigurable Array of Gates with Outrageous Network-delays. In Jonathan W. Greene, Jason Helge Anderson, editors, Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA 2017, Monterey, CA, USA, February 22-24, 2017. pages 85-94, ACM, 2017. [doi]
@inproceedings{GiesenRGD17,
title = {Quality-Time Tradeoffs in Component-Specific Mapping: How to Train Your Dynamically Reconfigurable Array of Gates with Outrageous Network-delays},
author = {Hans Giesen and Raphael Rubin and Benjamin Gojman and André DeHon},
year = {2017},
url = {http://dl.acm.org/citation.cfm?id=3026124},
researchr = {https://researchr.org/publication/GiesenRGD17},
cites = {0},
citedby = {0},
pages = {85-94},
booktitle = {Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA 2017, Monterey, CA, USA, February 22-24, 2017},
editor = {Jonathan W. Greene and Jason Helge Anderson},
publisher = {ACM},
isbn = {978-1-4503-4354-1},
}