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Gianluca Giustolisi, Gaetano Palumbo. Design of CMOS three-stage amplifiers for near-to-minimum settling-time. Microelectronics Journal, 107:104939, 2021. [doi]
Possibly Related PublicationsThe following publications are possibly variants of this publication: Three-Stage Dynamic-Biased CMOS Amplifier With a Robust Optimization of the Settling TimeGianluca Giustolisi, Gaetano Palumbo. tcas, 62-I(11):2641-2651, 2015. [doi] Robust design of CMOS amplifiers oriented to settling-time specificationGianluca Giustolisi, Gaetano Palumbo. ijcta, 45(10):1329-1348, 2017. [doi]
The following publications are possibly variants of this publication: