Standard CMOS Implementation of a Multiple-Valued Logic Signed-Digit Adder Based on Negative Differential-Resistance Devices - researchr publication

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Alejandro F. González, Mayukh Bhattacharya, Shriram Kulkarni, Pinaki Mazumder. Standard CMOS Implementation of a Multiple-Valued Logic Signed-Digit Adder Based on Negative Differential-Resistance Devices. In ISMVL. pages 323, 2000. [doi]

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