Christopher J. Gonzalez, Eric Fluhr, Daniel Dreps, David Hogenmiller, Rahul M. Rao, Jose Paredes, Michael S. Floyd, Michael A. Sperling, Ryan Kruse, Vinod Ramadurai, Ryan Nett, Md. Saiful Islam, Juergen Pille, Donald W. Plass. 3.1 POWER9™: A processor family optimized for cognitive computing with 25Gb/s accelerator links and 16Gb/s PCIe Gen4. In 2017 IEEE International Solid-State Circuits Conference, ISSCC 2017, San Francisco, CA, USA, February 5-9, 2017. pages 50-51, IEEE, 2017. [doi]
@inproceedings{GonzalezFDHRPFS17,
title = {3.1 POWER9™: A processor family optimized for cognitive computing with 25Gb/s accelerator links and 16Gb/s PCIe Gen4},
author = {Christopher J. Gonzalez and Eric Fluhr and Daniel Dreps and David Hogenmiller and Rahul M. Rao and Jose Paredes and Michael S. Floyd and Michael A. Sperling and Ryan Kruse and Vinod Ramadurai and Ryan Nett and Md. Saiful Islam and Juergen Pille and Donald W. Plass},
year = {2017},
doi = {10.1109/ISSCC.2017.7870255},
url = {http://dx.doi.org/10.1109/ISSCC.2017.7870255},
researchr = {https://researchr.org/publication/GonzalezFDHRPFS17},
cites = {0},
citedby = {0},
pages = {50-51},
booktitle = {2017 IEEE International Solid-State Circuits Conference, ISSCC 2017, San Francisco, CA, USA, February 5-9, 2017},
publisher = {IEEE},
isbn = {978-1-5090-3758-2},
}