Design re-use for compile time reduction in FPGA high-level synthesis flows - researchr publication authors

researchr

You are not signed in
Sign in
Sign up

Marcel Gort, Jason Helge Anderson. Design re-use for compile time reduction in FPGA high-level synthesis flows. In Jialin Chen, Wenbo Yin, Yuichiro Shibata, Lingli Wang, Hayden Kwok-Hay So, Yuchun Ma, editors, 2014 International Conference on Field-Programmable Technology, FPT 2014, Shanghai, China, December 10-12, 2014. pages 4-11, IEEE, 2014. [doi]

This author has not been identified. Look up 'Marcel Gort' in GoogleThis author has not been identified. Look up 'Jason Helge Anderson' in Google

runs on WebDSL