OASIS: A 28-nm 32-kb SRAM-Based Computing-in-Memory Design With Output Activation Sparsity Support

Qingyu Guo, Nanbing Pan, Xin Qiao, Xiaoxin Cui, Yuan Wang 0001. OASIS: A 28-nm 32-kb SRAM-Based Computing-in-Memory Design With Output Activation Sparsity Support. IEEE Trans. Circuits Syst. II Express Briefs, 71(4):1899-1903, April 2024. [doi]

Abstract

Abstract is missing.