Pallav Gupta, Rui Zhang, Niraj K. Jha. Automatic Test Generation for Combinational Threshold Logic Networks. IEEE Trans. VLSI Syst., 16(8):1035-1045, 2008. [doi]
@article{GuptaZJ08,
title = {Automatic Test Generation for Combinational Threshold Logic Networks},
author = {Pallav Gupta and Rui Zhang and Niraj K. Jha},
year = {2008},
doi = {10.1109/TVLSI.2008.2000671},
url = {http://dx.doi.org/10.1109/TVLSI.2008.2000671},
tags = {testing, logic},
researchr = {https://researchr.org/publication/GuptaZJ08},
cites = {0},
citedby = {0},
journal = {IEEE Trans. VLSI Syst.},
volume = {16},
number = {8},
pages = {1035-1045},
}