José Pineda de Gyvez, Eric van de Wetering. Average Leakage Current Estimation of CMOS Logic Circuits. In 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April - 3 May 2001, Marina Del Rey, CA, USA. pages 375-379, IEEE Computer Society, 2001. [doi]
@inproceedings{GyvezW01, title = {Average Leakage Current Estimation of CMOS Logic Circuits}, author = {José Pineda de Gyvez and Eric van de Wetering}, year = {2001}, url = {http://csdl.computer.org/comp/proceedings/vts/2001/1122/00/11220375abs.htm}, tags = {logic}, researchr = {https://researchr.org/publication/GyvezW01}, cites = {0}, citedby = {0}, pages = {375-379}, booktitle = {19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April - 3 May 2001, Marina Del Rey, CA, USA}, publisher = {IEEE Computer Society}, isbn = {0-7695-1122-8}, }