Fazal Hameed, Jerónimo Castrillón. A Novel Hybrid DRAM/STT-RAM Last-Level-Cache Architecture for Performance, Energy, and Endurance Enhancement. IEEE Trans. VLSI Syst., 27(10):2375-2386, 2019. [doi]
@article{HameedC19,
title = {A Novel Hybrid DRAM/STT-RAM Last-Level-Cache Architecture for Performance, Energy, and Endurance Enhancement},
author = {Fazal Hameed and Jerónimo Castrillón},
year = {2019},
doi = {10.1109/TVLSI.2019.2918385},
url = {https://doi.org/10.1109/TVLSI.2019.2918385},
researchr = {https://researchr.org/publication/HameedC19},
cites = {0},
citedby = {0},
journal = {IEEE Trans. VLSI Syst.},
volume = {27},
number = {10},
pages = {2375-2386},
}