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Fazal Hameed, Jerónimo Castrillón. A Novel Hybrid DRAM/STT-RAM Last-Level-Cache Architecture for Performance, Energy, and Endurance Enhancement. IEEE Trans. VLSI Syst., 27(10):2375-2386, 2019. [doi]
Possibly Related PublicationsThe following publications are possibly variants of this publication: Efficient STT-RAM last-level-cache architecture to replace DRAM cacheFazal Hameed, Christian Menard, Jerónimo Castrillón. memsys 2017: 141-151 [doi] Performance and Energy-Efficient Design of STT-RAM Last-Level CacheFazal Hameed, Asif Ali Khan, Jerónimo Castrillón. tvlsi, 26(6):1059-1072, 2018. [doi]
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