B. P. Harish, Navakanta Bhat, Mahesh B. Patil. Process Variability-Aware Statistical Hybrid Modeling of Dynamic Power Dissipation in 65 nm CMOS Designs. In 2007 International Conference on Computing: Theory and Applications (ICCTA 2007), 5-7 March 2007, Kolkata, India. pages 94-98, IEEE Computer Society, 2007. [doi]
@inproceedings{HarishBP07:0,
title = {Process Variability-Aware Statistical Hybrid Modeling of Dynamic Power Dissipation in 65 nm CMOS Designs},
author = {B. P. Harish and Navakanta Bhat and Mahesh B. Patil},
year = {2007},
doi = {10.1109/ICCTA.2007.108},
url = {http://doi.ieeecomputersociety.org/10.1109/ICCTA.2007.108},
tags = {modeling, context-aware, process modeling},
researchr = {https://researchr.org/publication/HarishBP07%3A0},
cites = {0},
citedby = {0},
pages = {94-98},
booktitle = {2007 International Conference on Computing: Theory and Applications (ICCTA 2007), 5-7 March 2007, Kolkata, India},
publisher = {IEEE Computer Society},
isbn = {978-0-7695-2770-3},
}