A Two Stage Structure for High Order Multi-Bit Sigma-Delta ADC with Multiplier-less Digital Correction Logic

Baher Haroun, Chao Hua Wu. A Two Stage Structure for High Order Multi-Bit Sigma-Delta ADC with Multiplier-less Digital Correction Logic. In ISCAS. pages 9-12, 1994.

Authors

Baher Haroun

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Chao Hua Wu

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