A Two Stage Structure for High Order Multi-Bit Sigma-Delta ADC with Multiplier-less Digital Correction Logic

Baher Haroun, Chao Hua Wu. A Two Stage Structure for High Order Multi-Bit Sigma-Delta ADC with Multiplier-less Digital Correction Logic. In ISCAS. pages 9-12, 1994.

@inproceedings{HarounW94,
  title = {A Two Stage Structure for High Order Multi-Bit Sigma-Delta ADC with Multiplier-less Digital Correction Logic},
  author = {Baher Haroun and Chao Hua Wu},
  year = {1994},
  tags = {logic},
  researchr = {https://researchr.org/publication/HarounW94},
  cites = {0},
  citedby = {0},
  pages = {9-12},
  booktitle = {ISCAS},
}