A Computationally Efficient Reconfigurable Constant Multiplication Architecture Based on CSD Decoded Vertical-Horizontal Common Sub-Expression Elimination Algorithm - researchr publication authors

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Indranil Hatai, Indrajit Chakrabarti, Swapna Banerjee. A Computationally Efficient Reconfigurable Constant Multiplication Architecture Based on CSD Decoded Vertical-Horizontal Common Sub-Expression Elimination Algorithm. IEEE Trans. on Circuits and Systems, 65-I(1):130-140, 2018. [doi]

This author has not been identified. Look up 'Indranil Hatai' in GoogleThis author has not been identified. Look up 'Indrajit Chakrabarti' in GoogleThis author has not been identified. Look up 'Swapna Banerjee' in Google

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