A Computationally Efficient Reconfigurable Constant Multiplication Architecture Based on CSD Decoded Vertical-Horizontal Common Sub-Expression Elimination Algorithm - researchr publication

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Indranil Hatai, Indrajit Chakrabarti, Swapna Banerjee. A Computationally Efficient Reconfigurable Constant Multiplication Architecture Based on CSD Decoded Vertical-Horizontal Common Sub-Expression Elimination Algorithm. IEEE Trans. on Circuits and Systems, 65-I(1):130-140, 2018. [doi]

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