A Computationally Efficient Reconfigurable Constant Multiplication Architecture Based on CSD Decoded Vertical-Horizontal Common Sub-Expression Elimination Algorithm - researchr publication related

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Indranil Hatai, Indrajit Chakrabarti, Swapna Banerjee. A Computationally Efficient Reconfigurable Constant Multiplication Architecture Based on CSD Decoded Vertical-Horizontal Common Sub-Expression Elimination Algorithm. IEEE Trans. on Circuits and Systems, 65-I(1):130-140, 2018. [doi]

The following publications are possibly variants of this publication:

An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter SynthesisIndranil Hatai, Indrajit Chakrabarti, Swapna Banerjee. tcas, 62-I(4):1071-1080, 2015. [doi]

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