An area-efficient analog VLSI architecture for state-parallel Viterbi decoding - researchr publication

researchr

You are not signed in
Sign in
Sign up

Kai He, Gert Cauwenberghs. An area-efficient analog VLSI architecture for state-parallel Viterbi decoding. In International Symposium on Circuits and Systems (ISCAS 1999), May 30 - June 2, 1999, Orlando, Florida, USA. pages 432-435, IEEE, 1999. [doi]

Abstract is missing.

runs on WebDSL