An optimal and processor efficient parallel sorting algorithm on a linear array with a reconfigurable pipelined bus system

Min He, Xiaolong Wu, Si-Qing Zheng. An optimal and processor efficient parallel sorting algorithm on a linear array with a reconfigurable pipelined bus system. Computers & Electrical Engineering, 35(6):951-965, 2009. [doi]

Authors

Min He

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Xiaolong Wu

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Si-Qing Zheng

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