Min He, Xiaolong Wu, Si-Qing Zheng. An optimal and processor efficient parallel sorting algorithm on a linear array with a reconfigurable pipelined bus system. Computers & Electrical Engineering, 35(6):951-965, 2009. [doi]
@article{HeWZ09-2,
title = {An optimal and processor efficient parallel sorting algorithm on a linear array with a reconfigurable pipelined bus system},
author = {Min He and Xiaolong Wu and Si-Qing Zheng},
year = {2009},
doi = {10.1016/j.compeleceng.2008.11.020},
url = {http://dx.doi.org/10.1016/j.compeleceng.2008.11.020},
researchr = {https://researchr.org/publication/HeWZ09-2},
cites = {0},
citedby = {0},
journal = {Computers & Electrical Engineering},
volume = {35},
number = {6},
pages = {951-965},
}