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Min He, Xiaolong Wu, Si-Qing Zheng. An optimal and processor efficient parallel sorting algorithm on a linear array with a reconfigurable pipelined bus system. Computers & Electrical Engineering, 35(6):951-965, 2009. [doi]
Possibly Related PublicationsThe following publications are possibly variants of this publication: Fast and Processor Efficient Parallel Matrix Multiplication Algorithms on a Linear Array With a Reconfigurable Pipelined Bus SystemKeqin Li, Yi Pan, Si-Qing Zheng. tpds, 9(8):705-720, 1998. [doi] Optimal Sorting Algorithms for a Simplified 2D Array with Reconfigurable Pipelined Bus SystemMin He, Xiaolong Wu, Si-Qing Zheng, Burkhard Englert. tpds, 21(3):303-312, 2010. [doi]
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