Verifying SystemC Using Intermediate Verification Language and Stateful Symbolic Simulation

Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler. Verifying SystemC Using Intermediate Verification Language and Stateful Symbolic Simulation. IEEE Trans. on CAD of Integrated Circuits and Systems, 38(7):1359-1372, 2019. [doi]

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