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Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler. Verifying SystemC Using Intermediate Verification Language and Stateful Symbolic Simulation. IEEE Trans. on CAD of Integrated Circuits and Systems, 38(7):1359-1372, 2019. [doi]
Possibly Related PublicationsThe following publications are possibly variants of this publication: Verifying SystemC using an intermediate verification language and symbolic simulationHoang M. Le, Daniel Große, Vladimir Herdt, Rolf Drechsler. dac 2013: 116 [doi] Verifying SystemC using stateful symbolic simulationVladimir Herdt, Hoang M. Le, Rolf Drechsler. dac 2015: 49 [doi]
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