Diagnosis of Transistor Shorts in Logic Test Environment

Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Sin-ya Kobayashi, Yuzo Takamatsu. Diagnosis of Transistor Shorts in Logic Test Environment. In 15th Asian Test Symposium, ATS 2006, Fukuoka, Japan, November 20-23, 2006. pages 354-359, IEEE, 2006. [doi]

@inproceedings{HigamiSTKT06-0,
  title = {Diagnosis of Transistor Shorts in Logic Test Environment},
  author = {Yoshinobu Higami and Kewal K. Saluja and Hiroshi Takahashi and Sin-ya Kobayashi and Yuzo Takamatsu},
  year = {2006},
  doi = {10.1109/ATS.2006.260955},
  url = {https://doi.org/10.1109/ATS.2006.260955},
  researchr = {https://researchr.org/publication/HigamiSTKT06-0},
  cites = {0},
  citedby = {0},
  pages = {354-359},
  booktitle = {15th Asian Test Symposium, ATS 2006, Fukuoka, Japan, November 20-23, 2006},
  publisher = {IEEE},
  isbn = {0-7695-2628-4},
}