Diagnosis of Gate Delay Faults in the Presence of Clock Delay Faults

Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja. Diagnosis of Gate Delay Faults in the Presence of Clock Delay Faults. In IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2014, Tampa, FL, USA, July 9-11, 2014. pages 320-325, IEEE, 2014. [doi]

Authors

Yoshinobu Higami

This author has not been identified. Look up 'Yoshinobu Higami' in Google

Hiroshi Takahashi

This author has not been identified. Look up 'Hiroshi Takahashi' in Google

Shin-ya Kobayashi

This author has not been identified. Look up 'Shin-ya Kobayashi' in Google

Kewal K. Saluja

This author has not been identified. Look up 'Kewal K. Saluja' in Google