Intra-Masking Dual-Rail Memory on LUT Implementation for SCA-Resistant AES on FPGA

Anh Tuan Hoang, Takeshi Fujino. Intra-Masking Dual-Rail Memory on LUT Implementation for SCA-Resistant AES on FPGA. TRETS, 7(2):10, 2014. [doi]

Authors

Anh Tuan Hoang

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Takeshi Fujino

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