Intra-Masking Dual-Rail Memory on LUT Implementation for SCA-Resistant AES on FPGA

Anh Tuan Hoang, Takeshi Fujino. Intra-Masking Dual-Rail Memory on LUT Implementation for SCA-Resistant AES on FPGA. TRETS, 7(2):10, 2014. [doi]

Abstract

Abstract is missing.