The following publications are possibly variants of this publication:
- Multiple sleep modes leakage control in peripheral circuits of a all major SRAM-based processor unitsHouman Homayoun, Avesta Sasan, Aseem Gupta, Alexander V. Veidenbaum, Fadi J. Kurdahi, Nikil Dutt. cf 2010: 297-308 [doi]
- MZZ-HVS: Multiple Sleep Modes Zig-Zag Horizontal and Vertical Sleep Transistor Sharing to Reduce Leakage Power in On-Chip SRAM Peripheral CircuitsHouman Homayoun, Avesta Sasan, Alexander V. Veidenbaum, Hsin-Cheng Yao, Shahin Golshan, Payam Heydari. tvlsi, 19(12):2303-2316, 2011. [doi]
- Reducing leakage power in peripheral circuits of L2 cachesHouman Homayoun, Alexander V. Veidenbaum. iccd 2007: 230-237 [doi]
- Adaptive techniques for leakage power management in L2 cache peripheral circuitsHouman Homayoun, Alexander V. Veidenbaum, Jean-Luc Gaudiot. iccd 2008: 563-569 [doi]
- ZZ-HVS: Zig-zag horizontal and vertical sleep transistor sharing to reduce leakage power in on-chip SRAM peripheral circuitsHouman Homayoun, Mohammad A. Makhzan, Alexander V. Veidenbaum. iccd 2008: 699-706 [doi]