Fractional-N DPLL-Based Low-Power Clocking Architecture for 1-14 Gb/s Multi-Standard Transmitter

Masum Hossain, Waleed El-Halwagy, A. K. M. Delwar Hossain, Aurangozeb. Fractional-N DPLL-Based Low-Power Clocking Architecture for 1-14 Gb/s Multi-Standard Transmitter. J. Solid-State Circuits, 52(10):2647-2662, 2017. [doi]

Abstract

Abstract is missing.