A PVT-insensitive all digital CMOS time-to-digital converter based on looped delay-line with extension scheme - researchr publication authors

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Siliang Hua, Donghui Wang, Leiou Wang, Yan Liu, Jiarui Li. A PVT-insensitive all digital CMOS time-to-digital converter based on looped delay-line with extension scheme. In 2015 IEEE 11th International Conference on ASIC, ASICON 2015, Chengdu, China, November 3-6, 2015. pages 1-4, IEEE, 2015. [doi]

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