Siliang Hua, Donghui Wang, Leiou Wang, Yan Liu, Jiarui Li. A PVT-insensitive all digital CMOS time-to-digital converter based on looped delay-line with extension scheme. In 2015 IEEE 11th International Conference on ASIC, ASICON 2015, Chengdu, China, November 3-6, 2015. pages 1-4, IEEE, 2015. [doi]
@inproceedings{HuaWWLL15,
title = {A PVT-insensitive all digital CMOS time-to-digital converter based on looped delay-line with extension scheme},
author = {Siliang Hua and Donghui Wang and Leiou Wang and Yan Liu and Jiarui Li},
year = {2015},
doi = {10.1109/ASICON.2015.7517127},
url = {https://doi.org/10.1109/ASICON.2015.7517127},
researchr = {https://researchr.org/publication/HuaWWLL15},
cites = {0},
citedby = {0},
pages = {1-4},
booktitle = {2015 IEEE 11th International Conference on ASIC, ASICON 2015, Chengdu, China, November 3-6, 2015},
publisher = {IEEE},
isbn = {978-1-4799-8485-5},
}