The following publications are possibly variants of this publication:
- Clock Period Minimization with Minimum Leakage PowerShih-Hsu Huang, Hua-Hsin Yeh, Yow-Tyng Nieh. todaes, 21(1):9, 2015. [doi]
- Minimum Inserted Buffers for Clock Period MinimizationShih-Hsu Huang, Guan-Yu Jhuo, Wei-Lun Huang. jise, 27(5):1513-1526, 2011. [doi]
- Clock period minimization with minimum area overhead in high-level synthesis of nonzero clock skew circuitsWen-Pin Tu, Shih-Hsu Huang, Chun-Hua Cheng. aspdac 2012: 245-250 [doi]
- Register binding for clock period minimizationShih-Hsu Huang, Chun-Hua Cheng, Yow-Tyng Nieh, Wei-Chieh Yu. dac 2006: 439-444 [doi]