The following publications are possibly variants of this publication:
- A 177mW 10GS/s NRZ DAC with Switching-Glitch Compensation Achieving > 64dBc SFDR and < -77dBc IM3Hung-Yi Huang, Xin-Yu Chen, Tai-Haur Kuo. vlsic 2020: 1-2 [doi]
- 2 162-mW DAC Achieving >65 dBc SFDR and < -70 dBc IM3 at 10 GS/s With Output Impedance Compensation and Concentric Parallelogram RoutingHung-Yi Huang, Tai-Haur Kuo. jssc, 55(9):2478-2488, 2020. [doi]
- A 16-Bit 4.0-GS/s Calibration-Free 65 nm DAC Achieving >70 dBc SFDR and < -80 dBc IM3 Up to 1 GHz With Enhanced Constant-Switching-Activity Data-Weighted-AveragingYushen Fu, Chengyu Huang, Longqiang Lai, Nan Sun, Xueqing Li, Huazhong Yang. tcasI, 70(5):1856-1867, May 2023. [doi]
- A 12 bit 1 GS/s Dual-Rate Hybrid DAC With an 8 GS/s Unrolled Pipeline Delta-Sigma Modulator Achieving > 75 dB SFDR Over the Nyquist BandShiyu Su, Tu-I. Tsai, Praveen Kumar Sharma, Mike Shuo-Wei Chen. jssc, 50(4):896-907, 2015. [doi]
- A 12-Bit 2 GS/s Dual-Rate Hybrid DAC With Pulse-Error Pre-Distortion and In-Band Noise Cancellation Achieving > 74 dBc SFDR and <-80 dBc IM3 up to 1 GHz in 65 nm CMOSShiyu Su, Mike Shuo-Wei Chen. jssc, 51(12):2963-2978, 2016. [doi]
- A 14b 750MS/s DAC in 20nm CMOS with <-168dBm/Hz noise floor beyond Nyquist and 79dBc SFDR utilizing a low glitch-noise hybrid R-2R architectureSang Min Lee, Dongwon Seo, Shahin Mehdizad Taleie, Derui Kong, Michael Joseph McGowan, Tongyu Song, Ganesh R. Saripalli, Jenny Kuo, Seyfi S. Bazarjani. vlsic 2015: 164 [doi]
- A 14b 1GS/s DAC with SFDR > 80 dBc across the whole nyquist band by mixed total 3-dimesional sort-and-combine and dynamic element matchingShuo Huang, Xuan Li, Xiaoyong Li. asicon 2015: 1-4 [doi]
- A 12b 1.6GS/s 40mW DAC in 40nm CMOS with >70dB SFDR over entire Nyquist bandwidthWei-te Lin, Tai-Haur Kuo. isscc 2013: 474-475 [doi]